Air gap semiconductor structure and method of manufacture

ABSTRACT

An air gap semiconductor structure and corresponding method of manufacture. The method includes providing a substrate having metallic lines thereon. A high molecular weight sacrificial film is formed over the substrate. A portion of the high molecular weight sacrificial layer is removed to form spacers. A dielectric layer is formed over the substrate, the top surface of the metallic lines and the spacers. Finally, a thermal dissociation operation is conducted to remove the spacers, thereby forming an air pocket on each sidewall of the metallic lines.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan applicationserial no. 89127061, filed Dec. 18, 2000.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to a metal-oxide-semiconductor structureand corresponding method of manufacture. More particularly, the presentinvention relates to an air gap semiconductor structure andcorresponding method of manufacture.

2. Description of Related Art

Following the rapid reduction of semiconductor line width, theaccompanied increase in resistor-capacitor (RC) time delay has greatlyreduced the operating speed of integrated circuits. To reduce RC timedelay, methods that can lower resistance is frequently adopted. The mostcommon trend now is to replace conventional aluminum wires by copperwires.

A second way of reducing RC time delay is to reduce capacitance betweenconductive wires in a multi-layer design. Conventional silicon dioxideis no longer versatile enough for this purpose because silicon dioxidehas a relatively high dielectric constant. In general, low dielectricconstant organic or inorganic material is used to form inter-metaldielectric layers. However, a medium having the lowest dielectricconstant is air (a dielectric constant of 1). Therefore, air is an idealdielectric medium for lowering the capacitance of a capacitor.

Although air is the best dielectric material for lowering capacitance,overall mechanical strength of the device is reduced correspondingly. Aweakened structure can have serious effects in various aspects ofsubsequent integrated circuit fabrication.

FIG. 1 is a schematic cross-sectional view showing a conventionalsemiconductor device that uses air as a dielectric medium. As shown inFIG. 1, the structure includes a metallic line 102 over a substrate 100.A silicon dioxide layer 104 is attached to the upper surface of themetallic line 102, thereby forming air pockets 106 and 108 that alsoserve as a dielectric layer.

In the aforementioned implementation, the metallic lines 102 are usuallyseparated from each other by a distance. Air pockets such as 108 maydestabilize the semiconductor structure leading to ultimate deformation.Moreover, the air pockets 106 and 108 are normally distributed all overthe substrate 100. Although capacitors have low capacitance when air isused as a dielectric medium layer, the poor heat conductivity of airoften results in a rapid rise in temperature during operation.

SUMMARY OF THE INVENTION

Accordingly, one object of the present invention is to provide an airgap semiconductor structure and corresponding method of manufacture. Themethod includes providing a substrate having metallic lines thereon. Ahigh molecular weight sacrificial film is formed over the substrate. Aportion of the high molecular weight sacrificial layer is removed toform spacers. A dielectric layer is formed over the substrate, the topsurface of the metallic lines and the spacers. Finally, a thermaldissociation operation is conducted to remove the spacers, therebyforming an air pocket on each sidewall of the metallic lines.

In this invention, the air gaps in this invention only form on thesidewall of the metallic lines. Conventional dielectric material fillsthe other portions of the substrate. With this arrangement,resistor-capacitor delay is reduced and operating speed of theintegrated circuit is increased. Yet, the substrate has sufficientmechanical strength to support other structures.

In addition, because only spacer-like air gaps are formed on thesidewalls of the metallic lines, heat generated by the device can easilybe conducted away to the surroundings. Hence, heat dissipation problemis minimized.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary, and are intended toprovide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention. In the drawings,

FIG. 1 is a schematic cross-sectional view showing a conventionalsemiconductor device that uses air as a dielectric medium; and

FIGS. 2 through 5 are schematic cross-sectional views showing theprogression of steps for producing an air gap semiconductor deviceaccording to one preferred embodiment of this invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to the present preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numbers areused in the drawings and the description to refer to the same or likeparts.

FIGS. 2 through 5 are schematic cross-sectional views showing theprogression of steps for producing an air gap semiconductor deviceaccording to one preferred embodiment of this invention. As shown inFIG. 2, a substrate 200 having a plurality of metallic lines 202 thereonis provided. A high molecular weight sacrificial layer 204 is formedover the metallic lines 202 and the substrate 200. The high molecularweight sacrificial layer 204 has a low dissociation temperature ofbetween 300° C. to 400° C. The sacrificial layer 204 can bepolynorbornene formed, for example, by spinning. The substrate 200 canbe a semiconductor substrate that includes a plurality of metallic linelayers.

As shown in FIG. 3, a portion of the high molecular weight sacrificiallayer 204 is removed by back etching to form high molecular weightspacers 204 a on the sidewalls of the metallic lines 202.

As shown in FIG. 4, a dielectric layer 206 is formed over the substrate200, the metallic lines 202 and the high molecular weight spacers 204 a.The dielectric layer 206 can be a silicon dioxide layer formed, forexample, by plasma-enhanced chemical vapor deposition (PECVD) orspin-on-glass (SOG) method.

As shown in FIG. 5, the substrate 200 is put inside a furnace and bakedso that the high molecular weight spacers 204 a dissociate to form smallmolecular weight side products (not shown). The side products diffuseinto the dielectric layer 206, thereby forming air pockets 208 in theoriginal high molecular spacers 204 a locations. A temperature of around400° C. to 450° C. is used in the furnace to dissociate the highmolecular weight sacrificial layer.

In conclusion, the advantages of the invention includes:

1. The air gaps in this invention only form on the sidewall of themetallic lines. Conventional dielectric material fills the otherportions of the substrate. With this arrangement, resistor-capacitordelay is reduced and operating speed of the integrated circuit isincreased. Yet, the substrate has sufficient mechanical strength tosupport other structures.

2. Since only small spacer-like air gaps are formed on the sidewalls ofthe metal lines, heat generated by the device can easily be conductedaway to the surroundings. Hence, the heat dissipation problem isminimized.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

What is claimed is:
 1. A method of manufacturing a semiconductor devicehaving an air packet, comprising the steps of: providing a substratehaving a plurality of metallic lines thereon; forming a sacrificiallayer over the substrate and the metallic lines; defining thesacrificial layer to form spacers on the sidewalls of the metalliclines, wherein the substrate between the spacers of two metallic linesis exposed; forming a dielectric layer on the exposed substrate, themetallic lines and the spacers; and removing the spacers to form airpockets instead of the spacers.
 2. The method of claim 1, wherein thesacrificial layer is a high molecular compound that can thermallydissociate at a temperature of between 300° C. to 430° C.
 3. The methodof claim 2, wherein the step of forming the sacrificial layer includesdepositing polynorbomene.
 4. The method of claim 1, wherein the step offorming the sacrificial layer includes spin-coating.
 5. The method ofclaim 1, wherein the step of removing a portion of the sacrificial layerincludes back etching.
 6. The method of claim 1, wherein the step ofremoving the spacers includes the sub-steps of: dissociating the spacermaterial by heating to form side products; and permitting the sideproducts to diffuse away via the dielectric layer.
 7. The method ofclaim 6, wherein the temperature for dissociating the spacer material isset between 400° C. to 450° C.
 8. The method of claim 1, wherein thesubstrate is a semiconductor substrate that has a plurality of metalliclayers.
 9. The method of claim 1, wherein the step of forming thedielectric layer includes chemical vapor deposition.
 10. The method ofclaim 1, wherein the step of forming the dielectric layer includes aspin-on-glass (SOG) operation.
 11. The method of claim 1, wherein thestep of forming the dielectric layer includes depositing silicondioxide.
 12. A semiconductor device having an air spacer, comprising: asubstrate having a plurality of spaced metallic lines thereon; and adielectric layer covering the metallic lines and filled between themetallic lines, with a plurality of air spacers interposed between thedielectric layer and the sidewalls of the metallic lines.
 13. The deviceof claim 12, wherein the substrate includes a semiconductor substratethat has a plurality of interconnect layers.
 14. The device of claim 12,wherein the dielectric layer is a silicon dioxide layer formed byplasma-enhanced chemical vapor deposition.
 15. The device of claim 12,wherein the dielectric layer is a silicon dioxide layer formed by aspin-coating process.
 16. A method of manufacturing a semiconductordevice having an air pocket, comprising: providing a substrate having aplurality of metallic lines thereon; forming a sacrificial layer overthe substrate and the metallic lines; etching back the sacrificial layerto form spacers on the sidewalls of the metallic lines and to expose thesubstrate between the spacers of two metallic lines; forming adielectric layer on the exposed substrate, the metallic lines and thespacers; and removing the spacers to form air pockets instead of thespacers.
 17. The method of claim 16, wherein the sacrificial layer is ahigh molecular compound that can thermally dissociate at a temperatureof between 300° C. to 430° C.
 18. The method of claim 17, wherein thestep of forming the sacrificial layer includes depositing polynorbomene.19. The method of claim 16, wherein the step of forming the sacrificiallayer includes spin-coating.
 20. The method of claim 16, wherein thestep of removing the spacers includes the substeps of: dissociating thespacer material by heating to form side products; and permitting theside products to diffuse away via the dielectric layer.
 21. The methodof claim 20, wherein the temperature for dissociating the spacermaterial is set between 400° C. to 450° C.
 22. The method of claim 16,wherein the substrate is a semiconductor substrate that has a pluralityof metallic layers.
 23. The method of claim 16, wherein the step offorming the dielectric layer includes chemical vapor deposition.
 24. Themethod of claim 16, wherein the step of forming the dielectric layerincludes a spin-on-glass (SOG) operation.
 25. The method of claim 16,wherein the step of forming the dielectric layer includes depositingsilicon dioxide.